In recent years, the operation frequency band for mobile communication such as for mobile phones has been made higher, so that a PLL circuit operable at a high-frequency band is required as well, which includes a prescaler that is used for such mobile communication. Then, a method for avoiding misoperation due to a delay time has been proposed. Referring now to FIG. 1, the configuration of a dual-modulus prescaler for avoiding a delay time shown in JP S62(1987)-122323 A (page 2, FIG. 1) will be described below. In addition, the configuration of another conventional dual-modulus prescaler operating in a similar manner but having a configuration different from FIG. 1 will be described, with reference to FIG. 2 and a configuration of a conventional triple-modulus prescaler also will be described.
The conventional dual-modulus prescaler described in JP S62(1987)-122323 A, as shown in FIG. 1, is composed of D-type flip-flop (hereinafter abbreviated as DFF) circuits and logic circuits (NAND circuits). A clock signal that is input from a clock input terminal 11 is input through clock inputs of three DFF circuits 14a, 14b and 14c. A data input of the first DFF circuit 14a is connected to a Q output of the third DFF circuit 14c via a first input of a first NAND circuit 15a. A data input of the second DFF circuit 14b is connected to a NQ output of the third DFF circuit 14c via a first input of a second NAND circuit 15b. A second input of the second NAND circuit 15b is connected to a Q output of the first DFF circuit 14a. A data input of the third DFF circuit 14c is connected to a NQ output of the second DFF circuit 14b. Thus, one feedback loop is configured. By using a second input of the first NAND circuit 15a as a mode switching terminal 13, a control signal from the mode switching terminal 13 allows an output signal in two modes to be output from an output terminal 12, which is an output from the NQ output of the second DFF circuit 14b. ¼-frequency-division can be obtained by the mode switching terminal 13 at a low level, whereas ⅕-frequency-division can be obtained by the mode switching terminal 13 at a high level.
FIG. 2 shows a dual-modulus prescaler operating in the same manner as in FIG. 1, in which similarly to the prescaler of FIG. 1 three DFF circuits are provided. Instead of the two NAND circuits, one AND circuit and one OR circuit are used. A clock signal that is input from a clock input terminal 21 is input through clock inputs of the three DFF circuits 24a, 24b and 24c. A data input of the first DFF circuit 24a is connected to a Q output of the third DFF circuit 24c via a first input of a first AND circuit 25. A data input of the second DFF circuit 24b is connected to the Q output of the third DFF circuit 24c via a first input of a first OR circuit 26. A second input of the first OR circuit 26 is connected to a Q output of the first DFF circuit 24a. A data input of the third DFF circuit 24c is connected to a NQ output of the second DFF circuit 24b. Thus, one feedback loop is configured. By using a second input of the first AND circuit 25 as a mode switching terminal 23, a control signal from the mode switching terminal 23 allows an output signal in two modes to be output from an output terminal 22, which is an output from the NQ output of the second DFF circuit 24b. ¼-frequency-division can be obtained by the mode switching terminal 23 at a low level, whereas ⅕-frequency-division can be obtained by the mode switching terminal 23 at a high level.
The triple-modulus prescaler is, as shown in FIG. 3, configured with two DFF circuits, two AND circuits, one OR circuit and one NOR circuit added to the dual-modulus prescaler shown in FIG. 2. A clock signal that is input from a clock input terminal 31 is input through clock inputs of three DFF circuits 34a, 34b and 34c. A data input of the first DFF circuit 34a is connected to a Q output of the third DFF circuit 34c via a first input of a first AND circuit 35a. A data input of the second DFF circuit 34b is connected to the Q output of the third DFF circuit 34c via a first input of a first OR circuit 36a. A second input of the first OR circuit 36a is connected to a Q output of the first DFF circuit 34a. A data input of the third DFF circuit 34c is connected to a NQ output of the second DFF circuit 34b. Thus, a feedback loop is configured.
A clock input of a fourth DFF circuit 34d is connected to the NQ output of the second DFF circuit 34b. A data input of the fourth DFF circuit 34d is connected to a NQ output of the fourth DFF circuit 34d, whereby a feedback loop is configured with the fourth DFF circuit 34d. A clock input of a fifth DFF circuit 34e is connected to a Q output of the fourth DFF circuit 34d. A data input of the fifth DFF circuit 34e is connected to a NQ output of the fifth DFF circuit 34e, whereby a feedback loop is configured with the fifth DFF circuit 34e. A first input of a second AND circuit 35b is connected to the Q output of the fourth DFF circuit 34d. A first input of a third AND circuit 35c is connected to a Q output of the fifth DFF circuit 34e. A first input of a second OR circuit 36b is connected to an output of the second AND circuit 35b, and a second input thereof is connected to an output of the third AND circuit 35c. A first input of a first NOR circuit 37 is connected to an output of the second OR circuit 36b. A second input of the first AND circuit 35a is connected to an output of the first NOR circuit 37. Thus, one feedback loop is configured.
By using a second input of the first NOR circuit 37 as a first mode switching terminal 33a, a second input of the second AND circuit 35b as a second mode switching terminal 33b and a second input of the third AND circuit 35c as a third mode switching terminal 33c, output signals in three modes can be obtained from the Q outputs of the fourth and the fifth DFF circuits 34d and 34e as first and second outputs 32a and 32d, in accordance with control signals from the first, the second and the third mode switching terminals 33a, 33b and 33c. ⅛-, 1/9- and 1/10-frequency-division can be obtained from the output terminal 32a and 1/16-, 1/17- and 1/18-frequency-division can be obtained from the output terminal 32b. The frequency division numbers of the output signals corresponding to the control signals M1, M2 and M3 from the first, the second and the third mode switching terminals 33a, 33b and 33c are shown in Table 1.
TABLE 1Frequencydivision numbersM1M2M31/8 HHL1/9 LHL1/10LLL1/16HHH1/17LHH1/18LLH
The dual-modulus and triple-modulus prescalers can be configured as stated above.
FIG. 4 and FIG. 5 are timing diagrams of the prescaler circuit shown in FIG. 3, where FIG. 4 shows the case of the frequency division numbers of ⅛, 1/9 and 1/10 and FIG. 5 shows the case of the frequency division numbers of 1/16, 1/17 and 1/18. In the prescaler circuit shown in FIG. 3, output signals from the output terminals 32a and 32b of the prescaler circuit are input to a logic part, and modulus signals thereof are input to modulus signal input terminals 33a, 33b and 33c of the prescaler circuit. As shown in FIG. 4, a margin for misoperation when these signals are input to the second input of the first AND circuit 35a is within 7 clock signals at the time of switching from ⅛-frequency-division to 1/9-frequency-division, is within 3 clock signals at the time of switching from 1/9-frequency-division to 1/10-frequency-division and is within 3 clock signals at the time of switching from 1/10-frequency-division to ⅛-frequency-division. Further, as shown in FIG. 5, the margin is within 15 clock signals at the time of switching from 1/16-frequency-division to 1/17-frequency-division, is within 7 clock signals at the time of switching from 1/17-frequency-division to 1/18-frequency-division and is within 7 clock signals at the time of switching from 1/18-frequency-division to 1/16-frequency-division (outside the drawing).
In the prescaler circuit shown in FIG. 3, the smallest margin for misoperation is within 2 clocks. In the case of a clock frequency at 100 MHz, this corresponds to a margin for misoperation of 40 nsec, but in the case of a clock frequency at 2 GHz, the margin for misoperation becomes smaller up to 1 nsec. If a trend toward a higher frequency still continues in the future, the margin for misoperation further will be reduced. As currently possible countermeasures for this, a current in a circuit such as a DFF circuit is increased so as to shorten the total delay time to be kept within the margin for misoperation, or a DFF circuit is provided upstream of the modulus signal input terminal so as to enable the synchronization with the signal prior to the outputting from the prescaler circuit shown in FIG. 3, thus removing a delay time occurring in the logic. These circuit configurations enable the shortening of a delay time, but have the problem of an increase in current.